This application claims the benefit of Korean Application No. P2001-38130, filed in Korea on Jun. 29, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a reference circuit in a ferroelectric memory and a method for driving the same, which can stabilize the reference level and enable a reference capacitor to be commonly used by adjacent cell array blocks in order to reduce a layout area.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory device, (i.e., ferroelectric random access memory (FRAM)) has a data processing speed that is substantially the same as a dynamic random access memory (DRAM) and also retains data even in power-off. For this reason, the nonvolatile ferroelectric memory has been highly regarded as a next generation memory device.
As a memory device having a structure similar to that of a DRAM, FRAM uses a high residual polarization, which is a characteristic of ferroelectric, by using ferroelectric as a component of a capacitor. Due to such characteristic of a residual polarization, data remains unerased even if the electric field is removed.
FIG. 1 illustrates a hysteresis loop of a typical ferroelectric. As shown in FIG. 1, even if the electric field that induced a polarization is removed, the data is maintained at a certain amount (the xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states) due to the presence of the residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is constructed by regarding the xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states as xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively.
A related art ferroelectric memory device will now be explained with reference to the accompanying drawings. FIG. 2 is a schematic view of a cell array block of a typical ferroelectric memory, and FIG. 3 is a circuit diagram of a main cell in FIG. 2. The cell array block includes a plurality of sub cell arrays. Adjacent top and bottom sub cell arrays sub_T and sub_B are formed, and a sensing amplifier S/A block is formed between the sub cell arrays sub_T and sub_B. That is, one sensing amplifier circuit is correspondingly formed per each bit line, and a column selector CS is formed at the end of the bit line.
Each of the sub cell arrays includes bit line Top_B/L (or Bot_B/L), a plurality of main cells MC connected to the bit line Top_B/L (or Bot_B/L), a reference cell RC connected to the bit lines Top_B/L (or Bot_B/L), and a column selector CS. The column selector CS selectively activates a corresponding column bit line using Y (column) address. If the column selector CS is in the high level, the corresponding column bit line is connected to a data bus to enable data transmission.
The structure of a main cell of the cell array with the aforementioned structure will now be described. As shown in FIG. 3, a main cell MC is constructed such that a bit line B/T is formed in one direction, and a word line W/L is formed to cross the bit line. A plate line P/L is spaced apart from the word line W/L in the same direction as the word line W/L. A transistor T with a gate connected to the word line W/L and a source connected to the bit line B/L is formed. A ferroelectric capacitor FC is formed in such a manner that its first terminal is connected to a drain of the transistor T and its second terminal is connected to the plate line P/L.
The structure and operation of a related art reference cell of a ferroelectric memory with the aforementioned structure will now be described. FIG. 4 is a schematic view of a reference cell of the related art ferroelectric memory. In each reference cell, a bit line B/L is formed in one direction, a reference word line REF_W/L is formed to cross the bit line, a switch block 51 is controlled by a signal on the reference word line to selectively transmit a reference voltage stored in the ferroelectric capacitor bit line. Ferroelectric capacitors are connected to the input terminal of the switching block 51 in parallel. The level initializing block 52 selectively initializes a level of the input terminal of the switching block 51 connected to the ferroelectric capacitors.
The switching block 51 includes an NMOS transistor (also referred to as xe2x80x9cfirst transistorxe2x80x9d) T1 with a gate connected to the reference word line REF_W/L, a drain connected to the bit line B/L, and a source connected to a storage node SN.
The level initializing block 52 is controlled by a reference cell equalizer control signal REF_EQ, which is a control signal for initializing the storage node SN of the reference cell. The level initializing block 52 includes an NMOS transistor (also referred to as xe2x80x9csecond transistorxe2x80x9d) T2 connected between the source of the first transistor T1 and a ground terminal Vss.
The number of ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCn is determined depending on the capacitor size of the reference cell. The storage node SN is connected with first terminals of the ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCn in parallel. In other words, FC1 is a basic connection terminal, and FC2, FC3, FC4, . . . , FCn may be provided additionally depending on the need.
The reference cell equalizer control signal REF_EQ initializes the storage node to a ground voltage level. Namely, when the reference cell equalizer control signal REF_EQ is in the high level, the second transistor T2 is turned on so that the storage node is maintained at a ground voltage level.
The operation of the aforementioned reference cell will now be described. Qs and Qns of a hysteresis loop of a ferroelectric shown in FIG. 5 denote the switching charge of the ferroelectric capacitor and the non-switching charge of the ferroelectric capacitor, respectively. The reference cell is based on Qns. In other words, the reference word line REF_W/L within the operation cycle is raised to the high level together with the reference plate line REF_P/L. Accordingly, charges equivalent to the size of Qnsxc3x97(ferroelectric capacitor) are supplied to the bit line B/L. In this case, the reference word line REF_W/L is changed to the low level before the sensing amplifier is operated, so that the reference cell is not affected by a voltage of the bit line. Meanwhile, the reference plate line REF_P/L is maintained at the high level, and is changed to the low level when the reference word line is sufficiently stabilized.
As described above, since non-switching charges Qns are used, a separate restoring operation is not required during a precharge period. Accordingly, the high level in the reference word line REF_W/L is not required any longer than this.
Since the reference level is affected by an initial level of the storage node SN, the second transistor T2 of FIG. 4 is used to stabilize the storage node SN, and the reference equalizer control signal REF_EQ is used to initialize the storage node to the ground voltage level. Therefore, since the initial level of the storage is maintained at the ground voltage level, the reference level can be stabilized.
The method of operation will now be described with reference to a hysteresis loop and a timing chart of the reference cell. FIG. 5 is a hysteresis loop of the reference cell of the related art ferroelectric memory, and FIG. 6 is a timing chart illustrating the operation of a reference cell according to the related art. Referring to FIG. 6, an operation cycle begins as a chip enable signal CEBpad is changed to the low level, so that active periods A, B, and C are formed. A precharge period D begins as the chip enable signal CEBpad is changed to the level. One cycle is completed by passing through the precharge period.
When the active period of the chip begins, an address is decoded during the periods A and B. Then, various control signals are activated, and the reference word line REF_W/L and the reference plate line REF_P/L are changed from the low level to the high level. As the reference word line REF_W/L and the reference plate line REF_P/L are changed from the low level to the high level, the reference cell data are transmitted to each bit line in the period C.
Then, reference plate line REF_P/L is changed to the low level in the precharge period D. Therefore, by maintaining the low level in the remaining periods, the reference plate line REF_P/L is maintained at the low level, thereby preventing voltage to pass through the both electrodes of the reference cell in the ferroelectric capacitor. From a moment that the reference plate line REF_P/L is changed from the high level to the low level, the reference plate line REF_P/L is changed from the xe2x80x9caxe2x80x9d state to the xe2x80x9cbxe2x80x9d state as time passes.
Therefore, depending on a lapse of time after the reference plate line REF_P/L is changed from the high level to the low level, a non-destructive charge varies between the value Qns and the value Q""ns.
Due to such inconsistency of the non-destructive charge, the reference bit line REF_B/L level maintained by the non-destructive charge also varies accordingly. Therefore, due to the Qns and Q""ns values, the reference level varies inconsistently and so reduces the sensing margin.
The aforementioned ferroelectric memory device and method for driving a reference cell of the related art has the following disadvantages. Since the non-destructive charge is not constant, the reference bit line level is also changed. As a result, the reference level is not constant and changes under the influence of Qns and Q""ns, thereby reducing the sensing margin.
Particularly, time dependency has a large effect on a ferroelectric capacitor. This results in a variation in charge amount due to a charge and discharge time, which leads to a large change in the reference level.
In the related art ferroelectric memory device, only voltage is used to form a reference level, resulting in that the reference level is remarkably varied. In other words, the related art capacitor is highly dependent on time.
Accordingly, the present invention is directed to a reference circuit in a ferroelectric memory and a method for driving the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a reference circuit in a ferroelectric memory and a method for driving the same that can stabilize a reference level.
Another object of the present invention is to provide a reference circuit in a ferroelectric memory and a method for driving the same that enable a reference capacitor to be commonly used by adjacent cell array blocks in order to reduce a layout area.
Still another object of the present invention is to provide a reference circuit in a ferroelectric memory and a method for driving the same that can stabilize a reference level and enable a reference capacitor to be commonly used by adjacent cell array blocks in order to reduce a layout area.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a reference circuit in a ferroelectric according to one aspect of the present invention includes a reference plate line and a reference word line adjacently formed in a first direction in correspondence with a cell block including a plurality of unit cells, a plurality of bit lines connected to the unit cells and formed in a second direction, a plurality of parallel reference capacitors having a first electrode connected to the reference plate line and a second electrode connected to a storage node SN of a reference cell, an initializing unit connected to the storage node and initializing a level of the reference cell, and a switching block and formed between the bit line and the storage node in correspondence with the bit lines and controlled by signals applied to the reference word line.
In another aspect of the present invention, a method for driving a reference circuit of a ferroelectric memory includes transiting a chip enable signal CEBpad from high level to low level so as to activate a chip, transiting an applied signal of a reference plate line to low level at a starting point of an active period, controlling a pulse time of this period, and controlling an amount of linear Qns charge in the reference capacitor, simultaneously transiting applied signals of the reference word line and the reference plate line to high level at an ending point of reference capacitor charge and discharging the reference cell data to each bit line, controlling an amount of electric charges discharged to the bit lines by using the pulse time in a period maintaining high level of a reference word line and transiting an applied signal of the reference word line to low level, and transiting an active signal of a bit line sensing amplifier to high level at a point where the level of the reference word line is changed to low level.
In another aspect, the present invention provides a reference circuit in a ferroelectric memory, including a reference plate line and a reference word line adjacently formed in a first direction in correspondence with a cell block including a plurality of unit cells; a plurality of bit lines connected to the unit cells and formed in a second direction; a plurality of parallelly disposed reference capacitors each having a first electrode connected to the reference plate line and a second electrode connected to a storage node SN of a reference cell; an initializing unit connected to the storage node for initializing a level of the reference cell; and a switching block formed between the bit lines and the storage node in correspondence with the bit lines and controlled by signals applied to the reference word line.
In a further aspect, the present invention provides a method for driving a reference circuit of a ferroelectric memory, the method including the steps of changing a chip enable signal from a high level to a low level so as to activate a chip; changing a signal applied to a reference plate line to a low level at a starting point of an active period and maintaining said signal in the low level for a specified duration to control the amount of a linear charge Qns in a reference ferroelectric capacitor; simultaneously changing signals applied to a reference word line and the reference plate line to respective high levels at an ending point of said specified duration to discharge reference cell data to each bit line; changing the signal applied to the reference word line to a low level when a specified time has elapsed from said ending point of said specified duration to control the amount of electric charges discharged to the bit lines; and changing an active signal of a bit line sensing amplifier to a high level at substantially the same time as changing the signal applied to the reference word line to the low level.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.